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Does anyone in here know anything about SMT? Or even a website wherei can find out some information? Its really important, i have to put something about it in my report.
Cheers
Cheers
Make all cheques payable to:
F.M. Eister.
F.M. Eister.
Thanks FM, although its not quite what im looking for, its certainly along the right lines.
Cheers mate!
Cheers mate!
Manufacturing technology
Etching
During this process, material is selectively removed from the wafer surface as defined by the patterned photoresist in order to define the structure of the previously deposited layer. The etching process is accomplished by exposing the wafer to a gas plasma, which both chemically reacts with the material to be removed and physically ablates it. At the completion of etching, the remaining photoresist is cleared from the wafer.
A simplified process sequence
The basic fabrication process of an NMOS circuit can be used to illustrate how the process steps described above might be combined.
Preliminary to these steps is the cleaning of the single-crystal silicon wafer. The fabrication process gets under way with oxidation and nitridation, which are followed by application of the photoresist and photolithographic definition of the mask pattern for electrical isolation between circuit components. After the photoresist has been developed and the isolation oxide/nitride mask defined by etching, the wafer is ion-implanted to electrically isolate the areas where the MOSFETs are to be formed, and oxide is grown over the implanted regions. The oxide/nitride film is then removed, and a thin gate oxide is regrown in these regions, which are the sites for the MOS transistors. Polysilicon is deposited and patterned in the next photolithographic process using a second photomask to define the gate structure of the NMOS transistors. A subsequent ion-implantation process introduces the required impurities into the source/drain regions of the MOSFETs, and silicon oxide is deposited. The source/drain positions where electrical contact is to be made to the MOSFETs are defined, using the oxide-removal mask and an etch process. Metal is then deposited into the opened vias in the oxide layer and over its surface. During the subsequent photolithographic process, it is patterned to form the desired electrical interconnections. These two steps are repeated for each succeeding level to produce additional levels of interconnections. Finally, a protective overcoat of oxide/nitride is applied, and vias are opened so that the wires connecting the IC chip to its carrier package can be bonded to output pads. Although this basic process is drastically simplified, it illustrates the fundamentals of the manufacturing process.
The assembly process begins with an electrical test of the ICs die by die on each wafer prior to separation to determine the location of the good units. The wafer is then sawed into individual dies, and each good unit is installed in a plastic or ceramic package by attaching the die to a lead frame and soldering wires between the output pads on the die and the internal leads of the package. A final test is performed on the packaged die to determine whether the unit operates within the specified standards. These steps illustrate the relationship between the design process, which determines the character of the photomasks, and the manufacturing process.
In a 16M DRAM packaged in a molded plastic enclosure, the lead frame fingers are extended over the die, resulting in multiple short wire bonds to the die. This allows for efficient power distribution and reduction of noise on signal lines. This package is surface-mounted to a circuit card by “gluing” it in place prior to a flow soldering operation. This surface-mount technology replaces the earlier through-hole method of attachment, improving high-frequency performance while increasing the packing density and reliability as well as reducing the cost.
Source: Http://www.britannica.com
Search string: "Surface mount technology"
Search string: Etching
Etching
During this process, material is selectively removed from the wafer surface as defined by the patterned photoresist in order to define the structure of the previously deposited layer. The etching process is accomplished by exposing the wafer to a gas plasma, which both chemically reacts with the material to be removed and physically ablates it. At the completion of etching, the remaining photoresist is cleared from the wafer.
A simplified process sequence
The basic fabrication process of an NMOS circuit can be used to illustrate how the process steps described above might be combined.
Preliminary to these steps is the cleaning of the single-crystal silicon wafer. The fabrication process gets under way with oxidation and nitridation, which are followed by application of the photoresist and photolithographic definition of the mask pattern for electrical isolation between circuit components. After the photoresist has been developed and the isolation oxide/nitride mask defined by etching, the wafer is ion-implanted to electrically isolate the areas where the MOSFETs are to be formed, and oxide is grown over the implanted regions. The oxide/nitride film is then removed, and a thin gate oxide is regrown in these regions, which are the sites for the MOS transistors. Polysilicon is deposited and patterned in the next photolithographic process using a second photomask to define the gate structure of the NMOS transistors. A subsequent ion-implantation process introduces the required impurities into the source/drain regions of the MOSFETs, and silicon oxide is deposited. The source/drain positions where electrical contact is to be made to the MOSFETs are defined, using the oxide-removal mask and an etch process. Metal is then deposited into the opened vias in the oxide layer and over its surface. During the subsequent photolithographic process, it is patterned to form the desired electrical interconnections. These two steps are repeated for each succeeding level to produce additional levels of interconnections. Finally, a protective overcoat of oxide/nitride is applied, and vias are opened so that the wires connecting the IC chip to its carrier package can be bonded to output pads. Although this basic process is drastically simplified, it illustrates the fundamentals of the manufacturing process.
The assembly process begins with an electrical test of the ICs die by die on each wafer prior to separation to determine the location of the good units. The wafer is then sawed into individual dies, and each good unit is installed in a plastic or ceramic package by attaching the die to a lead frame and soldering wires between the output pads on the die and the internal leads of the package. A final test is performed on the packaged die to determine whether the unit operates within the specified standards. These steps illustrate the relationship between the design process, which determines the character of the photomasks, and the manufacturing process.
In a 16M DRAM packaged in a molded plastic enclosure, the lead frame fingers are extended over the die, resulting in multiple short wire bonds to the die. This allows for efficient power distribution and reduction of noise on signal lines. This package is surface-mounted to a circuit card by “gluing” it in place prior to a flow soldering operation. This surface-mount technology replaces the earlier through-hole method of attachment, improving high-frequency performance while increasing the packing density and reliability as well as reducing the cost.
Source: Http://www.britannica.com
Search string: "Surface mount technology"
Search string: Etching
Looks like id better keep searching by myself.....
Surface Mount Technology
SMT stands for...?
Does anyone in here know anything about SMT? Or even a website wherei can find out some information? Its really important, i have to put something about it in my report.
Cheers
Cheers